Instruction Scheduler for Multi Thread GPGPU
As for processors like GPGPU with many SPs, massive amount of calculation is processed in parallel. However, the commands processed in each SP are different, therefore, to solve this issue, the Instruction Scheduler to distribute the commands appropriately is required. The Instruction Scheduler schedules the commands i..
Automatic 128 channel De-skewing 4~9Gbps Transceiver for GDDR4 BOST (Built-Out Self Test) Data Sheet
An automatic 128 channel de-skewing 4~9Gbps transceiver for GDDR4 BOST(Built-Out Self Test) is fabricated in a 65nm CMOS technology. The proposed de-skewing transceiver matches the signal transition timing between channels so that despite of many channels’ conditions, lengths, received datum at the receive pad are ar..
Multi-banked Non-blocking Cache Memory for GPGPU
memory operation systems is improve the processing of memory operations which is slower than other operation. The multi-banked structure design has efficiency of cache operation because multiple threads can simultaneously read and write data in the cache of SIMT based GPGPU. Non-blocking structure design can reduce mis..
Resistive-Switching-Memory Driven By Low Power
The resistive switching properties driven by low voltage in a nano-scale resistive-random-access-memory architecutre composed of Al(top)/TiO2-X/TiO2/Al(bottom).The device exhibits resistive-random-access-memory behavior consistent with a resistive switching properties, demonstrates an on/off ratio greater than 1000:1, ..
Block Memory for FPGA
Block Memory for FPGA was designed and fabricated with Hynix 90nm.
8T Dual Port SRAM Cell was used for this Block Memory for FPGA.
This Block Memory can support Single Port or Dual Port Operation and can support x1, x2, x4, x9, x18, x36 Various Memory Organization.
Operation frequency is 200MHz and Data Access time..