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Interface > SERDES
  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 4/810 IP Cores
    • 기업 IP
    • M

    Low power 3.52Gbps SerDes

    SerDes with 3.2Gbps to 3.8Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its..

    KC587H1040 | 2020-08-20

    • 기업 IP
    • N
    • M
    • T

    12.5Gbps multi-rate electronic dispersion compensator for DFP lasers

    This IP consists of a receiver, a transmitter, and a clock generator. RX is a digital based CDR with integrated EDC and LIA (limiting amplifier) functions. Its mode is re-configurable by register. The IP supports three mode, EDC, LIA, and CDR mode. EDC mode is used to compensate chirp dispersion by fiber length. EDC..

    KC512H0708 | 2015-10-28

    • 기업 IP
    • N
    • M
    • T

    100Gbps SerDes (Gearbox) IP

    This IP is 100Gbps SerDes PHY IP for high-speed interface network and could be applied data center or enterprise network dealing with high data traffic. This IP is compliant to IEEE802.3ba, world-first 100Gbps global standard. This IP is applicable to network equipment line card platform such as router or switch, also..

    KC512H0671 | 2015-06-09

    • 대학·연구소 IP
    • N
    • M
    • T

    4 Gb/s LPDDR4 Tx Low Power FIR Driver

    A low-power IO transceiver for application processor in smart phones will be developed in this project. By using TSPC-type FIR driver in Tx to remove ISI and maintaining a constant NRZ amplitude in Rx to meet BER spec, we achieve optimized power and improved per-pin data rate. We propose a new architecture and circuit..

    KU291H0586 | 2014-11-10