Low power 3.52Gbps SerDes
SerDes with 3.2Gbps to 3.8Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its..
12.5Gbps multi-rate electronic dispersion compensator for DFP lasers
This IP consists of a receiver, a transmitter, and a clock generator. RX is a digital based CDR with integrated EDC and LIA (limiting amplifier) functions.
Its mode is re-configurable by register. The IP supports three mode, EDC, LIA, and CDR mode. EDC mode is used to compensate chirp dispersion by fiber length.
100Gbps SerDes (Gearbox) IP
This IP is 100Gbps SerDes PHY IP for high-speed interface network and could be applied data center or enterprise network dealing with high data traffic. This IP is compliant to IEEE802.3ba, world-first 100Gbps global standard. This IP is applicable to network equipment line card platform such as router or switch, also..
4 Gb/s LPDDR4 Tx Low Power FIR Driver
A low-power IO transceiver for application processor in smart phones will be developed in this project. By using TSPC-type FIR driver in Tx to remove ISI and maintaining a constant NRZ
amplitude in Rx to meet BER spec, we achieve optimized power and improved per-pin data rate. We propose a new architecture and circuit..