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total: 2/810 IP Cores
    • T

    DisplayPort v.1.2 FAUX sink transmitter

    DisplayPort v.1.2 FAUX sink transmitter circuit is fabricated in a 0.11 um CMOS technology. Proposed transmitter consists of 10:1 serializer, phase locked loop for 720MHz clock, output driver. The reference clock comes from sink clock and data recovery (CDR) circuit because sink side does not have reference clock. The ..

    KS064H0269 | 2012-11-07

    • T

    DisplayPort v.1.2 FAUX Source Transmitter

    DisplayPort v.1.2 FAUX sink transmitter circuit is fabricated in a 0.11 um CMOS technology. Proposed transmitter consists of 10:1 serializer, phase locked loop (PLL) for 720MHz clock, output driver. The reference clock comes from sink clock and data recovery (CDR) circuit because sink side does not have reference clock..

    KS064S0265 | 2012-11-07