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total: 1/810 IP Cores
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    Transceiver for DisplayPort v1.1a

    The single-loop referenceless CDR with WPFD has advantages in terms of power and area over conventional dual-loop clock and data recovery schemes. In addition, the proposed CDR is designed to operate with half-rate clock, for further power reduction and easier design. The recovered clock jitters are 13.2psp-p and 1.57p..

    KU064H0170 | 2011-07-01