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  • 대학·연구소 IP
  • N관련된 신규용역가능
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total: 4/810 IP Cores
    • 대학·연구소 IP
    • T

    A 10-bit 20-MS/s CMOS asynchronous successive approximation register analog-to-digital converter

    10-bit 20-MS/s CMOS asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) with the features of low power consumption and small area. Generally, an asynchronous SAR ADC is an architecture that has the higher conversion rate compared with a synchronous SAR ADC architecture and consumes ..

    KU089H0490 | 2014-02-11

    • 대학·연구소 IP
    • T

    Reduced Sample and Hold (S/H) count 100MS/s 10-bit Pipeline Analog-to-Digital Converter

    A 100MS/s 10-bit pipelined analog-to-digital converter (ADC) is fabricated in a 0.13 um CMOS technology. The proposed pipelined ADC comprises of three consecutive 2.8 bit/stage multiplying digital-to-analog converters (MDAC) followed by a 4-bit flash converter. A MDAC for 2.8-bit/state N-bit pipeline ADC needs four uni..

    KU064H0431 | 2013-10-21

    • 대학·연구소 IP
    • N
    • M
    • T

    A 10b 150MS/s 0.40mm2 47.3mW 45nm CMOS A/D Converter

    10-bit 150MS/s pipeline ADC

    KU161H0400 | 2013-09-17

    • 대학·연구소 IP
    • T

    10bit 200M ADC

    This IP is an analog-to-digital converter (ADC) employing a Time-interleaed pipelined successive approximation register (SAR) architecture for low power consumption and small area. The proposed IP include an internal clock generator, a reference buffer and a current generator. The ADC is operated single clock at 1...

    KR024H0395 | 2013-07-31