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Interface > MIPI
  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 9/810 IP Cores
    • 기업 IP
    • N
    • M
    • T

    MIPI CSI-2 Receiver Controller

    The MIPI CSI-2 Receiver Controller IP is fully compliant to the MIPI Alliance Standard for Camera Serial Interface 2 specification Version 1.1. The IP can controll 1 clock lane of CIL-MCNN and up to 4 data lanes of CIL-MFEN and process data strem at the rate of 80Mbps~1.0Gbps from each data lane.The IP can be paired wi..

    KC586H0858 | 2017-02-17

    • 기업 IP
    • N
    • M
    • T

    MIPI CSI-2 Transmitter Controller

    The MIPI CSI-2 Transmitter Controller IP is fully compliant to the MIPI Alliance Standard for Camera Serial Interface 2 specification Version 1.1. The IP can controll 1 clock lane of CIL-MCNN and up to 4 data lanes of CIL-MFEN and process data strem at the rate of 80Mbps~1.0Gbps from each data lane.The IP can be paired..

    KC586H0857 | 2017-02-17

    • 기업 IP
    • N
    • M
    • T

    MIPI DSI Receiver Controller

    The MIPI DSI Receiver Controller IP is fully compliant to the MIPI Alliance Standard for Display Serial Interface specification Version 1.1. The IP can controll 1 clock lane of CIL-SCNN and up to 4 data lanes of CIL-SFAA and process data strem at the rate of 80Mbps~1.2Gbps from each data lane.The IP can be paired with ..

    KC586H0856 | 2017-02-17

    • 기업 IP
    • N
    • M
    • T

    MIPI D-PHY Receiver

    The MIPI D-PHY Receiver IP is fully compliant to the MIPI Alliance Standard for D-PHY specification Version 1.1. The IP incorperates 1 clock lane of CIL-SCNN and 4 data lanes of CIL-SFAA for data transmittion. Each data lane and clock lane can transmit date at the rate of 80Mbps~1.2Gbps. The IP can be paired with the M..

    KC586H0855 | 2017-02-17

    • 기업 IP
    • N
    • M
    • T

    MIPI D-PHY Transmitter

    The MIPI D-PHY Transmitter IP is fully compliant to the MIPI Alliance Standard for D-PHY specification Version 1.1. The IP incorperates PLL for hgh speed clock generation, 1 clock lane of CIL-MCNN and 4 data lanes of CIL-MFEN for data transmittion. Each data lane and clock lane can transmit date at the rate of 80Mbps~1..

    KC586H0854 | 2017-02-17