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total: 1/810 IP Cores
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    1GHz CPU Core

    As the embedded processor, this IP has 149 Instruction based on the load/store architecture. This IP has dual-issue in-order superscalar architecture for the instruction parallelism. The scoreboard is designed for dual-rail decode and in-order scheduling. Also This IP has Branch Prediction (BP) logic with 10-bit GHR ..

    KC024S0531 | 2014-07-15