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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 4/810 IP Cores
    • 기업 IP
    • M
    • T

    USB 1.1 PHY

    The 3.3v USB1.1 device PHY is capable of transmitting and receiving serial data at both full speed (12Mbit/s) and low speed (1.5Mbit/s) data rates. It is designed to meet standard logic to interface with the physical layer of the universal serial bus.

    KC022H1011 | 2019-11-19

    • 기업 IP
    • M

    USB 1.1 PHY

    The 3.3v USB1.1 device PHY is capable of transmitting and receiving serial data at both full speed (12Mbit/s) and low speed (1.5Mbit/s) data rates. It is designed to meet standard logic to interface with the physical layer of the universal serial bus.

    KC022H0968 | 2018-12-06

    • 대학·연구소 IP
    • T

    USB 1.1 full-speed device PHY

    USB 1.1 device PHY IP complies with the USB 1.1 specification and USB Transceiver Macrocell Interface (UTMI). USB 1.1 device IP is implemented by Verilog. This IP consists of SYNC generator/detector, bit sutffer/unstuffer, NRZI encoder/decoder, and Serializer/Deserializer. This IP accepts 60MHz clock as input. This IP ..

    KU227S0474 | 2013-12-12

    • 기업 IP
    • N
    • M
    • T

    USB1.1 Device PHY

    This USB1.1 device PHY complies with the USB1.1 specification. The device IP implements the USB macro cell for full-speed operation which is adopted in the most USB devices and hub applications. The USB1.1 device PHY carries out sync pattern generation, bit stuffing/removing, data encoding/decoding, and the USB packets..

    KC010H0243 | 2012-10-16