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  • 기업 IP
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  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 3/810 IP Cores
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    Fractional PLL(500~ 1120MHz)

    SHPLLD001 is developed as a PLL-based macro cell for clock generator. The VCO frequency is adjustable and the range is 500MHz to 1120MHz. Output frequency can be further programmed by output divider control to generate 25MHz to 560MHz clock with 50% duty.

    KC183H0806 | 2016-05-18

    • 기업 IP
    • N
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    1.5GHz SSCG PLL

    This PLL is implemented in the 0.13um CMOS process employing a linear voltage-controlled oscillator (VCO). The VCO uses ring type which has wide variable frequency range and produces clocks with accurate duty cycles and phase relationships by means of a high-speed fractional divider. The PLL of Modulus-Method achiev..

    KC193H0785 | 2016-04-20

    • 대학·연구소 IP
    • T

    Sprad Spectrum Clock Generator(SSCG) based on modulation profile

    A spread spectrum clock generator based on modulation profile is fabricated in a 55 nm CMOS technology. The proposed frequency spreading algorithm is down-spreading (maximum frequency is 1.8 GHz) using a digital sigma-delta modulator. Modulation rate is changed according to up/down counter value. We can avoid the edge ..

    KU064H0703 | 2015-09-22