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total: 7/810 IP Cores
    • 대학·연구소 IP
    • T

    All Digital Phase Locked Loop with Single stage TDC

    This work 1.45-2.9 GHz all digital phase locked loop(ADPLL) with combination of Bang-Bang Phase Frequency Detector(BBPFD) and single stage time-to-digital converter(TDC). Single stage TDC was designed in Vernier type used for fine control to reduce output jitter and provide controllable larger gain than merely using co..

    KU085H0826 | 2016-09-13

    • 대학·연구소 IP
    • T

    2.3GHz ~ 3GHz Fractional-N Synthesizer based on sub-sampling PLL

    This 2.3GHz ~ 3GHz fractional-N frequency synthesizer based on sub-sampling phase locked loop is fabricated in a 65 nm CMOS technology. The proposed synthesizer is composed of SS-PLL operating at 3GHz and the flying adder. The SS-PLL makes the clear 3GHz multi-phase signal and the flying adder synthesizes the fractiona..

    KU064H0543 | 2014-09-01

    • 대학·연구소 IP
    • T

    Spread spectrum clock generator based on sub-sampling phase locked loop

    A spread spectrum clock generator based on sub-sampling phase locked loop is fabricated in a 65 nm CMOS technology. The proposed frequency spreading algorithm is down-spreading (maximum frequency is 2.7 GHz) using an additional charge pump. Its current flows into the loop filter after SS-PLL locked and for exact spread..

    KU064H0436 | 2013-10-21

    • 대학·연구소 IP
    • T

    5.12GHz injection-locked phase locked loop

    A 5.12GHz injection-locked phase locked loop is fabricated in a 65 nm CMOS technology. The proposed architecture is composed of two blocks, ILPLL and DLL. DLL is used for multiplying injection frequency by adjusting the number of stages. And ILPLL is the conventional one. For the stable bandwidth of PLL, there are inpu..

    KU064H0430 | 2013-10-21

    • 대학·연구소 IP
    • T

    4.5GHz Injection locked all-digital PLL

    A 4.5GHz injection locked all digital phase locked loop is fabricated in a 0.65 um CMOS technology. In phase locked loop, there are two paths, proportional path and integral path to generate high quality clock and make overall loop stable. And also scheme of injection locked phase locked loop is generally known as sche..

    KU064H0429 | 2013-10-21