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  • 대학·연구소 IP
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total: 3/810 IP Cores
    • 대학·연구소 IP
    • T

    DDR3 DRAM Memory Controller

    The Memory Controller IP is memory interface that targets 1800Mps DDR3 DRAM. This IP does not include the PHY interface and only includes the memory request control logic. This IP is compatible with the PHY interface generated by Xilinx’s MIG. This IP consists of a user interface and a memory controller block. The us..

    KU384S0942 | 2018-04-13

    • 기업 IP
    • M

    LPDDR3/4,DDR3/4 Memory Controller

    This Ultra Low Power Double Data Rate 3/4 (LPDDR3/4) Memory Controller IP is designed for dynamic applications requiring low latency, high memory throughput and full programmability. This LPDDR3/4 Memory Contorller is already silicon proven and dramatically reduced the SoC power & size.

    KC603S0938 | 2018-02-20

    • 기업 IP
    • N
    • M
    • T

    DDR2 Controller

    The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR/DDR2 memory devices/modules and pro-vides a generic command interface to user applications. This core reduces the efforts required to integrate the DDR..

    KC193S0566 | 2014-09-10