Cascadable USI-T Receiver/Transmitter
Cascadable USI-T Receiver/Transmitter IP fully compliant to USI-T standard. The IP incorperates PLL for hgh speed clock generation, 2 USI-T RX lanes and 2 USI-T TX lanes for data transmittion. Each data lane and can transmit date rate of 1Gbps ~ 2Gbps. The IP can be cascades upto 30 ICs. With cascade function, IP is su..
Low power 3.52Gbps SerDes
SerDes with 3.2Gbps to 3.8Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its..
LIN(Local Interconnect Network) Controller with AMBA APB Interface
LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as a..
CAN(Controller Area Network) Controller with AMBA APB Interface
CAN (Controller Area network) is a robust vehicle bus standard designed to allow microcontrollers and devices to communicate with each others’ applications without a host computer. CAN controller was implemented in Verilog HDL, based on CAN ver. 2.0A. The implemented CAN controller was verified in FPGA, and it can be..
USB 1.1 PHY
The 3.3v USB1.1 device PHY is capable of transmitting and receiving serial data at both full speed (12Mbit/s) and low speed (1.5Mbit/s) data rates. It is designed to meet standard logic to interface with the physical layer of the universal serial bus.