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Low power 8Gbps SerDes
SerDes with 8.0Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its function w..
KC587H1055 | 2020-12-15
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HDMI 2.1 Transmitter
삼성 8n 공정에 구현된 HDMI 2.1 Transmitter with HDCP 2.3
KC3726S1049 | 2020-12-08
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LVDS Receiver
삼성 4n 공정에서 구현된 LVDS Receiver
KC3726H1048 | 2020-12-08
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Cascadable USI-T Receiver/Transmitter
Cascadable USI-T Receiver/Transmitter IP fully compliant to USI-T standard. The IP incorperates PLL for hgh speed clock generation, 2 USI-T RX lanes and 2 USI-T TX lanes for data transmittion. Each data lane and can transmit date rate of 1Gbps ~ 2Gbps. The IP can be cascades upto 30 ICs. With cascade function, IP is su..
KC586H1041 | 2020-08-20
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Low power 3.52Gbps SerDes
SerDes with 3.2Gbps to 3.8Gbps data rate consists of 32-to-1 serializer, 1-to-32 de-serializer, and PLL with LC-VCO. This IP adopts an asynchronous system with embedded clock in serial data, and its IO interface uses a CML type. For BER test verification, loop back path and feed-forward path were inserted in IP and its..
KC587H1040 | 2020-08-20