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Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches
The proposed bidirectional shift-register reduces the area and power consumption by replacing master-slave flip-flops and 2-to-1 multiplexers with the proposed bidirectional pulsed-latches and non-overlap delayed pulsed clock signals, and by using sub shift-registers and extra temporary storage latches.
KU127H1026 | 2020-01-14
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PLL 60to300MHz
PLLs have been developed as phase locked loops in a variety of applications.
The PLL generates 60~300MHz clock referenced at 8~20MHz.
The output clock frequency is selected by the resister M, N
“FOUT = FIN/M*N”
KC022H1007 | 2019-11-19
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Crystal OSC 32.768KHz
The device is the main oscillator for RTC block.
The crystal oscillator operates frequency is 32.768KHz.
It supports bypass mode and controls output driving capability control.
KC022H1006 | 2019-11-19
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Crystal OSC 3MHz to 20MHz
The device is the main oscillator for PLL input.
This crystal oscillator is designed to operate 3, 8, 12, 16 and 20MHz.
It supports bypass mode and controls output driving capability control “S”
KC022H1005 | 2019-11-19
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Crystal OSC 32.768KHz
The device is the main oscillator for RTC block.
The crystal oscillator operates frequency is 32.768KHz.
It supports bypass mode and controls output driving capability control. It consumes very low current.
KC022H0964 | 2018-12-06