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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 6/810 IP Cores
    • 기업 IP
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    MIPI D-PHY Receiver

    The MIPI D-PHY Receiver IP is fully compliant to the MIPI Alliance Standard for D-PHY specification Version 1.1. The IP incorperates 1 clock lane of CIL-SCNN and 4 data lanes of CIL-SFAA for data transmittion. Each data lane and clock lane can transmit date at the rate of 80Mbps~1.2Gbps. The IP can be paired with the M..

    KC586H0855 | 2017-02-17

    • 기업 IP
    • N
    • M
    • T

    MIPI D-PHY Transmitter

    The MIPI D-PHY Transmitter IP is fully compliant to the MIPI Alliance Standard for D-PHY specification Version 1.1. The IP incorperates PLL for hgh speed clock generation, 1 clock lane of CIL-MCNN and 4 data lanes of CIL-MFEN for data transmittion. Each data lane and clock lane can transmit date at the rate of 80Mbps~1..

    KC586H0854 | 2017-02-17

    • 기업 IP
    • N
    • M
    • T

    MIPI D-PHY

    The MIPI D-PHY enables significant extension of the interface bandwidth for more advanced applications. The MIPI D-PHY configuration consists of a clock signal and data signals. To Address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and ..

    KC183H0807 | 2016-05-18

    • 기업 IP
    • N
    • M
    • T

    DT-MIPI D-PHY TX

    This DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source- synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI-2). The High..

    KC567H0729 | 2016-01-18

    • 대학·연구소 IP
    • T

    A 2-Gb/s MIPI D-PHY transmitter with 8-to-1 serializer

    A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and 8-phase clock generator composed of a delay-locked loop (DLL). The pro..

    KU089H0511 | 2014-04-30