삼성 4n 공정에서 구현된 LVDS Receiver
sub-LVDS Rx PHY
This silicon-proven IP is a high-frequency sub-LVDS receiver (HF sub-LVDS), which is dedicated to low-voltage differential signalling.
sub-LVDS Tx PHY
This silicon-proven IP is a high-frequency sub-LVDS transmitter (HF sub-LVDS), which is dedicated to low-voltage differential signalling. The IP includes a high-speed driver, a wide-band phase-locked loop (PLL), a serializer, and built-in self test (BIST) function.
This IP is the Video signal transmission standard between Host and Flat Panel Display. It's Serialization of 24bit Video RGB data and 4bit Control data. It has 350mV Low voltage swing.
12~85MHz LVDS RX
This LVDS RX IP converts the four LVDS data Streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 85MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85MHz clock, the data throughput is 2.38 Gbits/s (297.5 Mbytes/sec)