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  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 11/810 IP Cores
    • 대학·연구소 IP
    • P

    Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

    The proposed bidirectional shift-register reduces the area and power consumption by replacing master-slave flip-flops and 2-to-1 multiplexers with the proposed bidirectional pulsed-latches and non-overlap delayed pulsed clock signals, and by using sub shift-registers and extra temporary storage latches.

    KU127H1026 | 2020-01-14

    • 대학·연구소 IP
    • T

    An 11bit Two Step TDC with 3-D Vernier Space

    This work use a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also include the redundancy and error-correction technique..

    KU085H0828 | 2016-09-13

    • 대학·연구소 IP
    • M
    • T

    Digital CDR with Analog DCO

    The CDR IP circuit for input SPDIF audio data. This IP can be adopt to other random data CDR functions. Designed with partially digital logic with Verilog-HDL(concurrent, structural modeling). IP also include GDS region for oscillator. For SPDIF data recovery, 2MHz to 35MHz output clock generated. Endurance for input m..

    KU359S0789 | 2016-04-23

    • 대학·연구소 IP
    • M
    • T

    Digital CDR with Digital DCO

    The CDR IP circuit for input SPDIF audio data. This IP can be adopt to other random data CDR functions. Designed with fully digital logic with Verilog-HDL(concurrent, structural modeling). For SPDIF data recovery, 2MHz to 35MHz output clock generated. Endurance for input maximum jitter is ±0.25UI.

    KU359S0788 | 2016-04-23

    • 대학·연구소 IP
    • N
    • M
    • T

    CDR

    A digital Auto-Frequency Calibration technique applied to 2.5 ~ 2.9 GHz clock and data recovery (CDR) is presented. A traditional CDR implemented by adding a frequency-locked loop in a phase-locked loop in order to achieve a sufficiently large dynamic range. The proposed structure achieves wide input data rate ra..

    KU085H0780 | 2016-04-20