The PLL have been developed as phase locked loops in a variety of applications. This PLL generates 60~300MHz clock referenced at 8~20MHz. The output clock frequency is selected by the resister M, N
“FOUT = FIN/M*N”
This 100MHz&125MHz PLL allows implementation of integer-N frequency synthesizers when used with an internal loop filter and external reference frequency.
It is designed in 130nm BCDMOS technology for automotive applications and consists of phase and frequency detector(PFD), charge pump(CP), analog loop filter, voltage..
All Digital Phase Locked Loop with Single stage TDC
This work 1.45-2.9 GHz all digital phase locked loop(ADPLL) with combination of Bang-Bang Phase Frequency Detector(BBPFD) and single stage time-to-digital converter(TDC). Single stage TDC was designed in Vernier type used for fine control to reduce output jitter and provide controllable larger gain than merely using co..
Fractional PLL(500~ 1120MHz)
SHPLLD001 is developed as a PLL-based macro cell for clock generator. The VCO frequency is adjustable and the
range is 500MHz to 1120MHz. Output frequency can be further programmed by output divider control to generate
25MHz to 560MHz clock with 50% duty.
1.5GHz SSCG PLL
This PLL is implemented in the 0.13um CMOS process employing a linear voltage-controlled oscillator (VCO).
The VCO uses ring type which has wide variable frequency range and produces clocks with accurate duty cycles and phase relationships by means of a high-speed fractional divider.
The PLL of Modulus-Method achiev..