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Analog & Mixed Signal > Power Management Circuit > POR
  • 기업 IP
  • 대학·연구소 IP
  • N관련된 신규용역가능
  • M수정/가공 판매가능
  • T기술지원 가능
  • P현 상태로만 판매가능
total: 2/810 IP Cores
    • 기업 IP
    • M

    POR

    The power on reset consists of a Schmitt trigger and simple logic for forced reset input, which is forced asynchronous reset. Output port is, that means it is high to set flip-flop in particular state.

    KC022H0965 | 2018-12-06

    • 기업 IP
    • T

    0.18um Power-On Reset

    The Power-on Reset generates a reset pulse as power supply. The power supply reaches a specified voltage level, VTR, it will create the reset signal or pulse width signal. By this reset signal, all the logic end up initializing its known state.

    KC081H0234 | 2012-10-16