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total: 15/810 IP Cores
    • 대학·연구소 IP
    • T

    DDR3 DRAM Memory Controller

    The Memory Controller IP is memory interface that targets 1800Mps DDR3 DRAM. This IP does not include the PHY interface and only includes the memory request control logic. This IP is compatible with the PHY interface generated by Xilinx’s MIG. This IP consists of a user interface and a memory controller block. The us..

    KU384S0942 | 2018-04-13

    • 기업 IP
    • M

    LPDDR3/4,DDR3/4 Memory Controller

    This Ultra Low Power Double Data Rate 3/4 (LPDDR3/4) Memory Controller IP is designed for dynamic applications requiring low latency, high memory throughput and full programmability. This LPDDR3/4 Memory Contorller is already silicon proven and dramatically reduced the SoC power & size.

    KC603S0938 | 2018-02-20

    • 대학·연구소 IP
    • P

    Multi-Channel eMMC Controller

    The Multi-Channel eMMC controller with AMBA APB, AXI4 interface is used to control eMMC devices. The eMMC controller has APB’s slave interfaces with 32bit data width for eMMC command and AXI’s Master interface with 64bit data width for eMMC data. Multiple channels can increase the data bandwidth.

    KU359S0873 | 2017-03-28

    • 대학·연구소 IP
    • P

    eMMC Controller

    The eMMC controller with AMBA APB, AXI4 interface is used to control eMMC devices. The eMMC controller has APB’s slave interfaces with 32bit data width for eMMC command and AXI’s Master interface with 64bit data width for eMMC data. Include 4 asynchronous FIFO, and AXI4 DMAC interface.

    KU359S0813 | 2016-05-23

    • 대학·연구소 IP
    • P

    200MT @ 100 MHz NV-DDR2 NAND Flash Controller for Xilinx 7-series FPGAs

    This flash memory controller supports NV-DDR2 interface, rates 200MT of bandwidth at 100MHz, and uses only 1400 LUTs based on Xilinx 7-series FPGAs. This IP can be applied for memory devices such as solid-state drives (SSDs), and directly embedded on a system-on-chips (SoCs).

    KU385S0761 | 2016-04-12