|
High Dynamic Range IP for DDI & AP
High Dynamic Range algorithm helps to make input image have the best contrast image. After
checking the brightness value information, this algorithm increases contrast value...
DDR SDRAM Memory Controller
The DDR SDRAM controller interfaces between DDR SDRAM and user logic. It performs DDR SDRAM
read and write access based on user requests. The DDR SDRAM transfer two bits of data for...
16CH 12b 5Msps ADC
SAR (Successive Approximation Register) ADC based on 0.13um CMOS process is implemented.
2.5V ~ 3.6V AVDD and 1.2V DVDD is used and Maximum conversion rate is 5MHz. Up to 16...
High Speed High Resolution 640MHz 12bit Sigma-Delta ADC
This IP is composed of two matched fully differential, high-speed, low-power delta sigma ADC cores,
designed in CMOS 65nm LP technology. This ADC is suitable for IQ receive channels...
|
