 128Kb Pseudo Dual Port Synchronous SRAM
SDS2CSRAM_16Kx8 is 131,072-bit Pseudo Dual-Port Synchronous Static Random Access Memory with
dual clocks. It is organized as 16K words of 8 bits and integrates address, data and control registers.
It is designed using 90nm process(HL90LP), SK-Hynix, and memory cell is composed of 6-transistor ...
DisplayPort / eDP RX IP
The eDP RX IP supports DisplayPort ver. 1.3 and eDP ver 1.4 that are presented by
VESA (Video Electronics Standards Association) standards. The IP consists of two major blocks which are
RX physical layer and link layer. The transmitted DP/eDP data signal from source is converted to digital ...
MIPI D-PHY Transmitter
T The MIPI D-PHY Transmitter IP is fully compliant to the MIPI Alliance Standard for D-PHY specification
Version 1.1. The IP incorperates PLL for hgh speed clock generation, 1 clock lane of
CIL-MCNN and 4 data lanes of CIL-MFEN for data transmittion. Each data lane and clock ...
VR 360 degree stitching IP
This IP is Image stitching IP for 360 degree panoramic image. For to make 360 VR image,
it required huge systemresource but this IP can stitch natural 360 image up to from 16 multi
video source with proper bus bandwidth and compact core size. |
