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  • No 103. Low Power DRAM Evolution

    • JEDEC Mobile and IoT Forum 2016
    • Osamu Nagashima
    • Micron Memory Japan

    [목차]

    1. Mainstream DRAM Datarate by Type and Year of Introduction
    2. Evolution of Mainstream DRAM Energy
    3. Typical Mobile Device Usage
    4. Near-Term Future
    5. LPDDR4X:I/O Energy Reduction
    6. LPDDR4X I/O
    7. LPDDR4X:I/O Energy Breakdown
    8. I/O vs.DRAM Core Energy
    9. The Future ? All About Power Efficiency
    10. Effect of Increasing Speed Capability
    11. Energy Cost for Higher Speeds
    12. Alternatives to LPDDR5 in Mobile Devices
    13. Attacking the Largest Component of DRAM Power
    14. DRAM DVFS?
    15. DRAM DVFS
    16. Two-Step DRAM DVFS
    17. Two-Step DRAM DVFS
    18. Future Challenges
    19. Heterogenous Memory Space
    20. Logic-to-Logic Signaling

  • No 102. UFS Logo Certification

    • JEDEC Mobile and IoT Forum 2016
    • Perry Keller
    • Keysight

    [목차]

    1. UFS is State of the Art
    2. UFS Works Today and Tomorrow
    3. UFS Interoperability Universe
    4. State-of-the-Art Compliance
    5. UFSA Compliance Program  Mission
    6. UFS Compliance Test  Specification
    7. UFS Certification Process

  • No 101. Embracing the Next Wave

    • JEDEC Mobile and IoT Forum 2016
    • Dokyun Kim
    • Samsung

    [목차]

    1. Stagnation or Leap Forward ?
    2. From Convergence to Divergence
    3. Changing Role, Enriching Mobile Eco
    4. Never Enough Performance
    5. Challenges in Mobile
    6. Breakthrough: Power Optimization
    7. Mobile DRAM, Keep Innovating
    8. IoT, Fast Growing but Fragmented
    9. Significances of IoT
    10. Potential Memory Growth Area
    11. Automotive, Next Big Thing in IoT
    12. Lifestyle Change
    13. Technology Caching Up Fast
    14. Challenges in IoT Era
    15. Break through with JEDEC
    16. Summary

  • No 100. Architectural Options for LPDDR4 Implementation in Your Next Chip Design

    • JEDEC Mobile and IoT Forum 2016
    • Marc Greenberg
    • Synopsys

    [목차]

    1. LPDDR4 is different from earlier JEDEC DRAM
    2. Ways to connect LPDDR4 multiple channels
    3. How to handle 2-die and 4-die packages
    4. Dividing memory traffic across channels
    5. Floorplanning and making connections
    6. Using LPDDR4 low power features
    7. Key features of an LPDDR4 solution

  • No 98. Next Generation of Mobile Storage : UFS and UFS Card

    • JEDEC Mobile and IoT Forum 2016
    • HeeChang Cho
    • Samsung Electronics

    [목차]

    1. Next Generation of Mobile Storage : UFS and UFS Card Accelerating Mobile Revolution
    2. Abstraction
    3. Mobile devices are increasing !
    4. Increasing connected devices !!
    5. Higher capacity required as well !!!
    6. Your Mobile life is
    7. I.e Advanced Mobile Storage is needed !!
    8. Answer is UFS !!!
    9. UFS is
    10. UFS is “Mobile SSD” !!!
    11. UFS Card is
    12. UFS, the Fastest Mobile Storage
    13. UFS, Less power consumption
    14. UFS : Advanced Interface Technology
    15. UFS : Advanced Interface Technology
    16. UFS, Queuing/Re-ordering
    17. UFS :: Optimal for multi-processing
    18. UFS :: Optimal for multi-processing
    19. UFS Card : Standardization in JEDEC
    20. UFS Card : Shape & Pins
    21. UFS Card : suitable for new OS, as well
    22. UFS Card: Lower power consumption
    23. UFS Card: Superiority
    24. UFS Card: Superiority - details
    25. Collaboration in Standard Organizations
    26. UFS position in Industry (In Linux and Wikipedia)
    27. eUFS & UFS Card : Future
    28. Benefits Summary of UFS Card to Industry
    29. Winner takes it all
    30. UFS Card :: Strong tool for taking mobile Market
    31. UFS Card :: Govern Removable Storage Market

     

  • No 97. VALUE-ADDED PACKAGING INTEGRATION FOR MOBILE AND WEARABLE APPLICATIONS

    • JEDEC Mobile and IoT Forum 2016
    • Wei H. Koh, PhD
    • Huawei Technologies Co. Ltd.

    [목차]

    1. VALUE-ADDED PACKAGING INTEGRATION FOR MOBILE AND WEARABLE APPLICATIONS
    2. PACKAGING SYSTEM PROPOSITION
    3. PACKAGING WHITE KNIGHT RESCUE
    4. OUTLINE
    5. VALUE-ADDED PACKAGING DRIVERS
    6. PSI: NEW “CINDERELLA”
    7. VERSATILE PACKAGING TECHNOLOGY
    8. PACKAGING SYSTEMS
    9. IF PACKAGES WERE WEARABLES
    10. MOBILE AND WEARABLE MARKETS
    11. ADVANCED PACKAGING PLATFORM
    12. WERABLE AND FITNESS DEVICES
    19. PoP/SOC in SAMSUNG S7
    20. APPLE A8/A9 PoP
    21. AMKOR PoP TECHNOLOGY
    22. SAMSUNG EPOP
    23. POP ISSUES/CHALLENGES
    24. HD-FOWLP
    25. MOTHER OF ALL FAN-OUTs: eWLB
    26. FOWLP INTEGRATION
    27. AMKOR SWIFT TECHNOLOGY
    28. TSMC INFO WLP/PoP
    29. SIP FOR WEARABLES
    30. RELIABILITY QUALIFICATION
    31. HIGH TEMPERATURE DYNAMIC WARPAGE
    32. WARPAGE-RELATED STANDARDS
    33. SPP-024 REQUIREMENT
    34. iNEMI HIGH TEMPERTURE WARPGAE DATA
    35. NEW SUGGESTION: RFR Level
    36. NEEDS/CHALLENGES
    37. SUMMARY/CONCLUSIONS

  • No 96. Electrical Biochip Reality or Hype?

    • 시스템 - 반도체포럼 세미나
    • 박영준 교수
    • 연세대학교

    [목차]

    1. Revenue vs. Market cap.
    2. What is the Electrical(CMOS) Biochip ?
    3. A short tutorial on semiconductor
    4. Bipolar Junction Transistor
    5. For electrons to escape, needs to lower…
    6. MOSFET: Metal oxide semiconductor
    7. What is the organic molecule ?
    8. DNA
    9. Electrical DNA sequencing; Using dNTP….
    10. C as the backbone: Peptide and protein
    11. Protein is the key: PSA as an example
    12. Cell as the unit of life: H2 carrier is NADH (FADH)
    13. Slight different scheme in handling energy
    14. Fuel cell uses H2 as the energy carrier
    15. In the inner membrane of Mitochondria….
    16. Calvin cycle is the NADH and FADH generator
    17. NADH (nicotinamide adenine dinucleotide)
    18. Switching is carefully done by series of ‘Proteins’
    19. Similar mechanism in Photosynthesis
    20. Biomarkers are many….
    21. Inflammatory AZ markers in the blood…
    22. CMOS Biochip
    23. CMOS based Platform; Transducer is the key
    24. Transducer is the key #1: ISFET type
    25. Transducer is the key #2: Floating gate type
    26. Case of InSilixia
    27. C and T chip on the CMOS Platform
    28. Electrical bio sensor chip: C and T chip
    29. Thin EDL and Screening layer
    30. Inducing Dielectric Regime in the Electrolyte…
    31. Using the transition of electric field;
    32. Transient simulation (0.2 V ? 1.0 V)
    33. Experimental verification
    34. Potential of Electrical Signal to Modify the Biochemistry
    35. Both the hybridization and Selectivity
    36. T chip based on a tunneling current
    37. Tunneling is very sensitive to Surface
    38. Tunneling under the pulse bias
    39. Conclusion
    40. Proposal of ‘BIOCON’ to turn Hype to reality

  • No 94. Precision Data Converters for EIS Applications (and Others)

    • Research IP Discovering 2015
    • 김진태 교수
    • 건국대학교

    [목차]

    1. Mixed-Signal Electronics Lab at KU
    2. List of Data Converters We Work On
    3. Top-Down Mixed-Signal Design Flow
    4. Electrochemical Impedance Spectroscopy
    5. Lock-In Detection
    6. Top-Level Block Diagram
    7. Direct Digital Frequency Synthesis
    8. DDFS Verification
    9. High-Speed D/A Converter
    10. Digital Calibration on High-Speed DAC
    11. High-Frequency Active Filter
    12. Receive Signal Chain
    13. ADC Performance
    14. List of Data Converters We Work On
    15. High-Speed Asynchronous SAR ADC
    16. Design Spec/Performance
    17. High-Speed Pipelined SAR ADC
    18. List of Data Converters We Work On
    19. Temperature-to-Digital Converter
    20. Performance/Specification
    21. Conclusion

  • No 93. Micropower ΔΣ ADC

    • Research IP Discovering 2015
    • 채영철 교수
    • 연세대학교

    [목차]

    1. IP 개요
    2. What is a Micropower ADC?
    3. Energy by Architecture
    4. SAR vs. ΔΣ
    5. Previous work
    6. ΔΣ ADC Benchmarks
    7. Design Target
    8. Design Target
    9. Modulator Topology
    10. MATLAB Simulink Model
    11. MATLAB Simulation (65k Points)
    12. Noise Analysis
    13. Integrator Output Swing
    14. Inverter based Integrator
    15. Process Variation (HM18EW)
    16. Simulation Results : TR-level
    17. Chip Layout
    18. Test Setup
    19. Measured PSD
    20. Dynamic Range : 20KHZ Bandwidth
    21. Dynamic Range : 24KHZ Bandwidth
    22. Benchmark
    23. Conclusion

  • No 90. Low-power ADCs from KS/s to GS/s Conversion-rates

    • Research IP Discovering 2015
    • 류승탁 교수
    • KAIST

    [목차]

    1. ADCs from MSICL
    2. 5V 30ms 102dB SNR Incremental ?Σ ADC  (Dongbu 0.18um)
    3. 0.6V 12b 10MS/s SAR ADC (TMSC 65nm)
    4. 1.8V 12b 100kS/s Single/Differential SAR ADC  (TSMC 0.18um)
    5. 10b 20MS/s I/Q channel SAR ADC (TSMC 40nm)
    6. 11b 50MS/s Nonbinary Asynchronous SAR ADC  (CMOS 28nm)
    7. 14b 50MS/s 6mW SAR ADC (Samsung 65nm)
    8. 7b 1GS/s 7.2mW SAR ADC (Samsung 45nm)
    9. 9b 0.9GS/s 10.8mW SAR ADC (Samsung 45nm)
    10. 10b 1.7GS/s 15.4mW SAR ADC (Samsung 45nm)
    11. 7b 2GS/s 20.7mW Flash ADC (Samsung 65nm)
    12. 6b 10GS/s 63mW TI Time-Domain 8x  Interpolating Flash ADC (TSMC 65nm)

  • No 89. 중국의 대전환, 한국의 대기회

    • 중국의 대전환, 한국의 대기회
    • 전병서 소장
    • 중국 경제금융연구소

    [목차]

     

    1. 시진핑의 China 2.0

    2. 정보대국 중국을 주목하라

    3. 중국 반도체산업의 대전환

    4. 중국반도체산업의 성장전략

    5. 한국 반도체산업의 시회는?

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